1. Technical Field
The present invention relates generally to phase-locked loop circuitry and more particularly to phase-locked loop circuitry using charge pumps with current mirror circuitry.
2. Description of Related Art
A phase-locked loop (PLL) is an electronic circuit with a voltage- or current-driven oscillator that is adjusted to match in phase (and thus lock on) the frequency of an input signal. In addition, PLLs are used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, and multiply or divide a frequency. PLLs are frequently used in wireless communications, particularly where signals are carried using amplitude modulation (AM), frequency modulation (FM) and phase modulation (PM). PLLs are more commonly used for digital data transmission, but can also be designed for analog information. Examples of applications for PLLs include frequency synthesizers for digitally-tuned radio receivers and transmitters, recovery of small signals that otherwise would be lost in noise lock-in amplifier, recovery of clock timing information from a data stream such as from a disk drive, clock multipliers, and dual-tone multi-frequency (DTMF) decoders, modems, and other tone decoders, for remote control and telecommunications.
FIG. 1 illustrates phase-locked loop (PLL) circuitry 100, according to the prior art. Phase-frequency detector (PFD) circuitry 110 generates an “up” signal 115 and a “down” signal 120 by comparing the phase difference of an input signal 105 to a feedback signal 160. The PFD circuitry 110 outputs the up signal 115 and the down signal 120 depending on whether or not the phase of the feedback signal 160 lags (needs to speed up) or leads (needs to slow down) when compared to the input signal 105. Charge pump circuitry 125 generates current pulses in a charge pump output signal 130 (e.g., to charge capacitors in loop filter circuitry 135) based on the up signal 115 and the down signal 120. The charge pump circuitry 125 generates the current pulses with a minimum pulse width. For example, when the input signal 105 and the feedback signal 160 have equal phase, the current pulses of the charge pump output signal 130 have equal width. With unequal phase, one of the current pulses of the charge pump output signal 130 is lengthened to correct the phase.
The loop filter circuitry 135 filters the charge pump output signal 130 and generates a filtered control signal 140. Voltage controlled oscillator (VCO) circuitry 145 generates an output signal 150 whose. frequency is determined by the voltage of the filtered control signal 140. The PLL circuitry 100 loops the output signal 150 back to the PFD circuitry 110 as the feedback signal 160. Optionally, frequency divider circuitry 155 is placed in the feedback path of the loop to generate the feedback signal 160 and to allow the output signal 150 to be a multiple of the input signal 105.
One problem that arises with the PLL circuitry 100 is that the magnitude of the current pulses that charge the loop filter circuitry 135 (e.g., current pulses of the charge pump output signal 130) is dependent on a variety of voltage sources. Some examples upon which the current pulses depend are power supply voltages and the voltage of the filtered control signal 140. Also, if circuitry in the PLL circuitry 100 is terminated to voltages not equidistant from the voltage of the filtered control signal 140, the current pulses for the charge pump output signal 130 may not have equal magnitude. Having unequal magnitude in the current pulses, either from voltage variations or termination mismatch, results in static phase offsets in the output of the PLLs.
The magnitude of the independent current pulses may also be adjusted to set the desired loop bandwidth. The loop bandwidth is the measure of the ability of the PLL circuitry 100 to lock onto the input signal 105 and to handle jitter. A high loop bandwidth provides a fast lock time and tracks jitter on the input signal 105, passing the jitter through to the output signal 150. A low loop bandwidth filters out the jitter of the input signal 105, but increases the lock time of the PLL circuitry 100. Typically, for a given capacitor in the loop filter circuitry 135, a smaller current for the charge pump output signal 130 produces a lower loop bandwidth and a larger current for the charge pump output signal 130 produces a higher loop bandwidth.
When determining the ideal loop bandwidth, noise performance is an important consideration. In most PLLs, the two primary noise sources that exist are noise from the VCO circuitry 145 (VCO noise) and reference noise. Each source of noise has conflicting loop bandwidth requirements to minimize the effects of the noise. VCO noise is due to thermal and shot noise in the VCO circuitry 145 and affects the output signal 150. VCO noise is usually dominant and is reduced by increasing the loop bandwidth (i.e., increasing the current output from the charge pump circuitry 125) which allows the PLL circuitry 100 to track low frequency noise (i.e., noise below the loop bandwidth) and compensate for the effect of the low frequency noise on the output signal 150. Typically, VCO noise drops off rapidly at higher frequencies, so the noise remaining above the loop bandwidth generally has little effect on the output signal 150.
Reference noise has multiple contributors such as jitter on the input signal 105, thermal noise in the charge pump circuitry 125, and supply noise associated with the voltage of the filtered control signal 140. In integer PLLs with a clean input signal 105 (i.e., no jitter), increasing the loop bandwidth reduces the effect of the thermal noise in the charge pump circuitry 125, which reduces reference noise. However, if the input signal 105 is noisy, a high loop bandwidth allows more of the reference noise to pass through to the output signal 150. Similarly, in certain types of PLLs, known as delta-sigma PLLs, the value of the feedback divider circuitry 155 may be varied dynamically, which produces noise similar to reference noise on a noisy input signal 105. The reference noise can dominate the VCO noise and therefore the minimum possible loop bandwidth is desired rather than increasing the loop bandwidth.
Two exemplary ways to minimize the loop bandwidth are to increase the size of capacitors used in the loop filter circuitry 135 and to decrease the magnitude of the current of the charge pump output signal 130. Because area is a major concern in many designs and large capacitors increase the area requirements, decreasing the magnitude of the current is usually chosen. To achieve loop bandwidths on the order of 100 kHz using integrated capacitors of a reasonable size, currents with magnitudes ranging down to 10 s of nanoamps may be necessary. Reducing the magnitude of the current may reduce noise (e.g., reference noise), however, many other challenges arise when attempting to generate very low currents, especially in deep submicron technologies.
In particular, with nanoampere currents, such as those used in the delta-sigma PLLs, current mismatch due to the Early effect (i.e., reduction of the width of the base in bipolar transistor due to the widening of the base-collector junction with increasing base-collector voltage) can be significant depending on the value of the voltage for the filtered control signal. Moreover, the magnitude of device leakage in deep submicron technologies is often significantly larger than the actual signals being generated. Any mismatch between the currents in the up signal 115 and the down signal 120 caused by the device leakage results in the static phase offset between the input signal 105 and the output signal 160. Additionally, the mismatch generally requires one of the up signal 115 and the down signal 120 to be “on” for more than the minimum required time which allows more noise to be injected into the loop.